Providse a standard method of modeling ASICs in VHDL.This method is aimed at providing efficient, accurate,and tool independent simulation suitable for large chip-level designs typical of those which are based on ASICs. This publication has the status of a double logo IEEE/IEC standard
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Edition: 1.0 Published: 10/07/2004 Number of Pages: 430 File Size: 1 file , 2.4 MB
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