Full Description

Scope

Add mutual exclusion semantics to the shared variable feature in VHDL.

Purpose

To address a language feature area that received a significant share of negative ballots and positive ballots with comments on the implementation during the successful VHDL 1076-1993 balloting. The working group was formed to attempt to reach concensus on a better implementation of the language feature.

Abstract

Revision Standard - Superseded.VHSIC Hardware Description Language (VHDL) is defined. VHDL is a formal notationintended for use in all phases of the creation of electronic systems. Because it is both machine read-able and human readable, it supports the development, verification, synthesis, and testing of hard-ware designs; the communication of hardware design data; and the maintenance, modification, andprocurement of hardware. Its primary audiences are the implementors of tools supporting the lan-guage and the advanced users of the language.

Product Details

Published: 12/29/2000 ISBN(s): 9780738133263 Number of Pages: 300 File Size: 1 file , 1.5 MB Product Code(s): STDSU94817